CVE-2020-0574 — Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions

Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.

01What is this vulnerability?

Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.

02Affected products

Vendor	Product	Versions
Intel	Intel(R) MAX(R) 10 FPGA	All versions, See advisory https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html

03Active exploitation status

Not currently listed on the CISA Known Exploited Vulnerabilities (KEV) catalog. EPSS is the best forward-looking signal — see the EPSS row above.

04Recommended remediation

• Patch to a fixed version listed in the vendor advisory (see references below).
• Mitigate with WAF rules, network egress filters, or feature flags where the patch is not yet available.
• Hunt historical logs for exploitation indicators — see Detection signatures below.

05Technical details

For the full vendor write-up, exploit chains, and reference implementations, see the references list in section 09.

06Detection signatures

Ask SARA in chat to draft a starting detection for this CVE in your stack of choice.

07Related CVEs

No directly-cited follow-up CVEs in the KB record for this advisory. The references list in section 09 carries the vendor cross-references.

08Timeline

• Published: 2020-03-12T20:52:29.000Z
• Last modified: 2024-08-04T06:02:52.194Z

09References

• www.intel.com — https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.…