An insufficient DRAM address validation in PMFW may allow a privileged attacker to read from an invalid DRAM address to SRAM, potentially resulting in data corruption or denial of service.
An insufficient DRAM address validation in PMFW may allow a privileged attacker to read from an invalid DRAM address to SRAM, potentially resulting in data corruption or denial of service.
| Vendor | Product | Versions |
|---|---|---|
| AMD | AMD Radeon™ RX 6000 Series Graphics Cards | AMD Software: Adrenalin Edition 23.12.1 (23.30.13.01) |
| AMD | AMD Radeon™ PRO W6000 Series Graphics Cards | AMD Software: PRO Edition 23.Q4 (23.30.13.03) |
Not currently listed on the CISA Known Exploited Vulnerabilities (KEV) catalog. EPSS is the best forward-looking signal — see the EPSS row above.
For the full vendor write-up, exploit chains, and reference implementations, see the references list in section 09.
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No directly-cited follow-up CVEs in the KB record for this advisory. The references list in section 09 carries the vendor cross-references.