Insufficient DRAM address validation in System Management Unit (SMU) may allow an attacker to read/write from/to an invalid DRAM address, potentially resulting in denial-of-service.
Insufficient DRAM address validation in System Management Unit (SMU) may allow an attacker to read/write from/to an invalid DRAM address, potentially resulting in denial-of-service.
| Vendor | Product | Versions |
|---|---|---|
| AMD | Ryzen™ 3000 series Desktop Processors “Matisse" | various |
| AMD | AMD Ryzen™ 5000 Series Desktop Processors “Vermeer” | various |
| AMD | AMD Ryzen™ Threadripper™ 3000 Series Processors “Castle Peak” HEDT | various |
| AMD | AMD Ryzen™ Threadripper™ PRO Processors “Castle Peak” WS SP3 | various |
| AMD | AMD Ryzen™ Threadripper™ PRO 3000WX Series Processors “Chagall” WS | various |
| AMD | 2nd Gen AMD EPYC™ Processors | various |
| AMD | 3rd Gen AMD EPYC™ Processors | various |
| AMD | AMD EPYC™ Embedded 7002 | various |
| AMD | AMD EPYC™ Embedded 7003 | various |
| AMD | AMD Ryzen™ Embedded 5000 | various |
| AMD | AMD EPYC™ Embedded 7002 | various |
| AMD | AMD EPYC™ Embedded 7003 | various |
Not currently listed on the CISA Known Exploited Vulnerabilities (KEV) catalog. EPSS is the best forward-looking signal — see the EPSS row above.
For the full vendor write-up, exploit chains, and reference implementations, see the references list in section 09.
Ask SARA in chat to draft a starting detection for this CVE in your stack of choice.
No directly-cited follow-up CVEs in the KB record for this advisory. The references list in section 09 carries the vendor cross-references.