Improper re-initialization of IOMMU during the DRTM event may permit an untrusted platform configuration to persist, allowing an attacker to read or modify hypervisor memory, potentially resulting in loss of confidentiality, integrity, and availability.
Improper re-initialization of IOMMU during the DRTM event may permit an untrusted platform configuration to persist, allowing an attacker to read or modify hypervisor memory, potentially resulting in loss of confidentiality, integrity, and availability.
| Vendor | Product | Versions |
|---|---|---|
| AMD | AMD EPYC™ 7003 Series Processors | MilanPI 1.0.0.B |
| AMD | AMD EPYC™ 9004 Series Processors | Genoa 1.0.0.8 |
| AMD | AMD EPYC™ Embedded 7003 Series Processors | EmbMilanPI-SP3 1.0.0.7 |
| AMD | AMD EPYC™ Embedded 9003 Series Processors | EmbGenoaPI-SP5 1.0.0.3 |
Not currently listed on the CISA Known Exploited Vulnerabilities (KEV) catalog. EPSS is the best forward-looking signal — see the EPSS row above.
For the full vendor write-up, exploit chains, and reference implementations, see the references list in section 09.
Ask SARA in chat to draft a starting detection for this CVE in your stack of choice.
No directly-cited follow-up CVEs in the KB record for this advisory. The references list in section 09 carries the vendor cross-references.