On-chip debug and test interface with improper access control in some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.
On-chip debug and test interface with improper access control in some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.
| Vendor | Product | Versions |
|---|---|---|
| n | a / 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX | some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX |
Not currently listed on the CISA Known Exploited Vulnerabilities (KEV) catalog. EPSS is the best forward-looking signal — see the EPSS row above.
For the full vendor write-up, exploit chains, and reference implementations, see the references list in section 09.
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No directly-cited follow-up CVEs in the KB record for this advisory. The references list in section 09 carries the vendor cross-references.